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Past Contests
2020 CAD Contest at ICCAD
(Chair: Ing-Chao Lin)
Overview of 2020 CAD Contest at ICCAD
X-value Equivalence Checking
Routing with Cell Movement
GPU Accelerated Logic Re-simulation
2019 CAD Contest at ICCAD
(Chair: Ulf Schlichtmann)
Overview of 2019 CAD Contest at ICCAD
Logic regression on high dimensional boolean space
System-level FPGA routing with timing division multiplexing technique
LEF/DEF based open-source global routing
2018 CAD Contest at ICCAD
(Chair: Mark Po-Hung Lin)
Overview of 2018 CAD Contest at ICCAD
Program-building for name mapping
Obstacle-aware on-track bus routing
Timing-aware fill insertion
2017 CAD Contest at ICCAD
(Chair: Myung-Chul Kim)
Overview of 2017 CAD Contest at ICCAD
Resource-aware patch generation
Net open location finder with obstacles
Multi-deck standard cell legalization and benchmarks
2016 CAD Contest at ICCAD
(Chair: Shih-Hsu Huang)
Overview of 2016 CAD Contest at ICCAD
Non-exact Projective NPNP Boolean Matching and benchmark suite
Large-scale identical fault search
Pattern classification for integrated circuit design space analysis and benchmark suite
2015 CAD Contest at ICCAD
(Chair: Natarajan Viswanathan)
Overview of 2015 CAD Contest at ICCAD
Large-scale equivalence checking and function correction and benchmark suite
Incremental timing-driven placement and benchmark suite
3D interlayer cooling optimized network
2014 CAD Contest at ICCAD
(Chair: Iris Hui-Ru Jiang)
Overview of 2014 CAD Contest at ICCAD
Simultaneous CNF encoder optimization with SAT solver setting selection and benchmark suite
incremental timing-driven placement and benchmark suite
Design for manufacturability flow for advanced semiconductor nodes and benchmark suite
2013 CAD Contest at ICCAD
(Chair: Zhuo Li)
Overview of 2013 CAD Contest at ICCAD
Technology mapping for macro blocks and benchmark suite
Placement finishing and benchmark suite
Mask optimization and benchmark suite
2012 CAD Contest at ICCAD
(Chair: Yih-Lang Li)
Finding the minimal logic difference for functional ECO and benchmark suite
Design hierarchy aware routability-driven placement and benchmark suite
Fuzzy pattern matching for physical verification and benchmark suite
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